Limitations and known issues
This tool only uses one interface window, so if a new one is open, the previous window will be replaced. The co-simulation implementation was verified in two Virtex 5 FPGAs (XC5VFX30T-2FF665 and XC5VFX130T-1FF1738). The developer team does not guarantee that it will work on other FPGAs. A Timing Constraint error may occur, while generating the co-simulation block due to different lengths of the internal paths.
Conditions of use
The developer team and the users of the application agree with the following terms:
- 1. The developer team will not be responsible for any direct or indirect damage caused to you or your machine when using the software application, whatever the reason may be.
- 2. Users are responsible for the use that they give to the product.
- 3. The developer team reserves the right to alter any feature or specification at any time.
If you disagree with any of these terms, do not use the application